하드웨어 엔지니어로 가는 길

[Clock_Divider.vhd]

-- 1Khz Clock Divider(period:1000us) from 50Mhz clock input(period: 20ns)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Clock_Divider is

port(

    clk, reset: in std_logic;

    clock_out: out std_logic

    );

end Clock_Divider;

architecture bhv of Clock_Divider is

signal count: integer := 1;

signal tmp: std_logic := '0'; -- clock_out의 작동 유무를 결정하는 변수

begin

process(clk, reset)

begin

    if(reset = '1') then

        count <= 1;

        tmp <= '0';

    elsif rising_edge(clk) then

        count <= count+1;

        if (count = 25000) then -- count가 1부터 시작됐기 때문에 24999가 아니라 25000이다.

            tmp <= NOT tmp;

            count <= 1;

        end if;

     end if;

clock_out <= tmp;

end process;

end bhv;

[clockdv_tb.vhd]

-- Testbench for 1Khz Clock Divider(period:1000us) from 50Mhz clock input

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY clockdv_tb IS

END clockdv_tb;

ARCHITECTURE behavioral OF clockdv_tb IS

COMPONENT Clock_Divider

PORT(

    clk : IN std_logic;

    reset : IN std_logic;

    clock_out : OUT std_logic

    );

END COMPONENT;

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal clock_out : std_logic;

-- Clock period definitions

constant clk_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Clock_Divider 

PORT MAP (

        clk => clk,

        reset => reset,

        clock_out => clock_out

        );

-- Clock process definitions

clk_process :process

begin

    clk <= '0';

wait for clk_period/2;

    clk <= '1';

wait for clk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

wait for 100 ns;

    reset <= '1';

wait for 100 ns;

    reset <= '0';

wait;

end process;

end;